A comparator circuit with a hysteresis characteristic is called a hysteresis comparator circuit, and is used for, e.g., a zero cross detection circuit. Such a zero cross detection circuit has been used as a delay detection circuit of receiving device.
In recent years, it is used as a modulator-demodulator circuit of mobile communication equipment, such as a portable telephone and PHS (personal handyphone system). In this use, required are such high sensitivity that can receive a weak signal and such low consumed power that can make the battery last a long time. An example of a hysteresis comparator circuit that complies with these requirements is disclosed in Japanese patent application laid-open No. 64-073906 (1989). This circuit is explained in detail below.
FIG. 1 shows the composition of the conventional hysteresis comparator circuit. Hereinafter, in transistors, PMOS means a p-type MOS (metal oxide semiconductor), and NMOS means n-type MOS.
The hysteresis comparator circuit is composed of input terminals 201, 202 and 203, a first differential input circuit 204 connected with these input terminals, an adder circuit 205, a current switching circuit 206, a PMOS transistor 207, a NMOS transistor 208 with a gate connected with the input terminal 203, a quantizer 209 and a NMOS transistor 210.
The output end of the quantizer 209 is connected with an output terminal 211. The NMOS transistor 210 has a gate connected with the input terminal 203 and a drain connected with the low-potential side of the current switching circuit 206. The adder circuit 205 is disposed between the first differential input circuit 204 and a high-potential power source 212. The gate of the PMOS transistor 207 is connected with output point B of the adder circuit 205. The input end of the quantizer 209 is the drains of the PMOS transistor 207 and the NMOS transistor 208.
The first differential input circuit 204 is composed of a NMOS transistor 204a with a gate connected with the input terminal 202, a NMOS transistor 204b with a gate connected with the input terminal 201, and a NMOS transistor 204c with a gate connected with the input terminal 203. The drain of the NMOS transistor 204c is connected with the sources of the NMOS transistor 204a, 204b. The adder circuit 205 is composed of PMOS transistors 205a, 205b that have gates connected commonly and have drains connected with the drains of the NMOS transistors 204a, 204b, respectively.
The current switching circuit 206 is composed of NMOS transistors 206a, 206b. The gate of the NMOS transistor 206a is connected with the output of the quantizer 209 and the output terminal 211. The sources of the NMOS transistors 206a, 206b are connected each other, and the drains thereof are connected with the drains of the PMOS transistors 205a, 205b. Further, the sources of the NMOS transistors 206a, 206b are connected with the drain of the NMOS transistor 210. The quantizer 209 is composed of two inverters 209a, 209b connected in series, and generates an output signal when a signal of higher than a certain level is input. The NMOS transistor 210 operates as a constant current source.
FIG. 2 shows operation waveforms of the hysteresis comparator circuit in FIG. 1. The first differential input circuit 204 and the adder circuit 205 form a comparator. As shown in FIG. 2 (a), reference voltage (V.sub.REF) is applied to the input terminal 201, input voltage V.sub.IN is applied to the input terminal 202, constant voltage (bias voltage) is applied to the input terminal 203, the NMOS transistors 204c, 208 and 210 each function as a constant current source. Here, when voltages at output points m, n of the adder circuit 205 are equal, i.e., when I.sub.1 and I.sub.2 to flow through the PMOS transistors 205a, 205b, respectively are equal, is the threshold value of comparator.
When as shown in FIG. 2 (a) the relation of V.sub.REF &gt;V.sub.IN is given, drain currents I.sub.a, I.sub.b flow through the NMOS transistors 204a, 204b as shown in FIG. 2 (d). In this gate, since the PMOS transistor 207 turns on and the input of the quantizer 209 is at H level, the output terminal 211 outputs output voltage V.sub.211 of H level as shown in FIG. 2 (a). Since the NMOS transistor 206a turns on inputting voltage V.sub.211 of the output terminal 211, drain current I.sub.o (=drain current .alpha. of the NMOS transistor 210) flows through the NMOS transistor 206a but does not flow through 206b.
Then, as shown in FIG. 2 (a), when V.sub.IN increases gradually and the relation of V.sub.IN &gt;V.sub.REF occurs at time point t.sub.1, drain current I.sub.c of the NMOS transistor 204a tends to increase and drain current I.sub.d of the NMOS transistor 204b tends to reduce. With this change, drain current I.sub.b of the PMOS transistor 205b starts reducing and the potential of point n starts lowering gradually. When it lowers to a certain value, voltage that the inverter 209a can start operating is input to the inverter 209a. This time point is t.sub.2, when the output of the inverter 209a turns into H level and the output of the inverter 209b turns into L level. Therefore, as shown in FIG. 2 (b), the NMOS transistor 206b turns into ON state, and at the same time, as shown in FIG. 2 (c), the NMOS transistor turns into OFF state. This time point (t.sub.2) when the output change occurs is later than time point t.sub.1 when V.sub.IN &gt;V.sub.REF occurs. Namely, a hysteresis characteristic is obtained. Hereupon, as shown in FIG. 2 (d), current I.sub.a, i.e., the sum of (drain current I.sub.c of the NMOS transistor 204a-drain current I.sub.f of the NMOS transistor 206b), flows through the PMOS transistor 205a of the adder circuit 205, and drain current I.sub.b of the PMOS transistor 205b reduces. Also, as shown in FIG. 2 (e), drain current .alpha. of the NMOS transistor 210 increases in response to the switching of NMOS transistors 204a and 204b.
Then, after the output terminal 211 becomes L level, as V.sub.IN starts reducing gradually, drain current I.sub.d of the NMOS transistor 204b starts increasing responsively and, on the contrary, drain current I.sub.c of the NMOS transistor 204a starts reducing. Then, at time point t.sub.3, it turns into V.sub.REF &gt;V.sub.IN. However, at time point t.sub.3, since the drain output of the PMOS transistor 207 does not increase up to such voltage that can make the quantizer 209 and the current switching circuit 206 operate, the inverter 209a does not come to operation. At time point t.sub.4 a little later than the time point when turned into V.sub.REF &gt;V.sub.IN, the input of the inverter 209a reaches H level, when the output of the inverter 209a turns into L level and the output of the inverter 209b turns into H level. Namely, the voltage level of the output terminal 211 turns from L level into H level. That this time point t.sub.4 is later than time point t.sub.3 shows a hysteresis characteristic is provided.
Thus, the comparator circuit in FIG. 1 conducts the hysteresis operation that when the start turns into V.sub.IN &gt;V.sub.REF or V.sub.REF &gt;V.sub.IN, the voltage level of the output terminal 211 changes delaying.
However, in the conventional hysteresis comparator circuit, when the output level of the quantizer 209 is high, the NMOS transistors 206a, 206b of the current switching circuit 206 exceed the linear region as a differential amplifier and as shown in FIGS. 2 (b), (c), operate as a switch to switch current. Therefore, the matching effect of transfer characteristic as a differential amplifier does not occur, and the hysteresis width is determined by drain current of the NMOS transistor 210 and the mutual conductance of the NMOS transistors 204a, 204b of the differential input circuit 204. Therefore, there is a problem that it is affected by characteristic variation of device due to the dispersion in device or the temperature. Furthermore, there is a problem that it is difficult to obtain the matching of response time between rinse signal and fall signal.